Semiconductor buried layer technology is widely used in manufacturing integrated circuit, in particular in integrated circuit process for triodes which have high performance requirements. With large scale integrated circuits and complex processes, the development of buried layer technology will influence the performance of integrated circuits and the development of fabrication processes.
The buried layer technology, which is mainly applied to the fabrication process of bipolar junction transistors (BJT), may reduce power loss and parasitic capacitance by reducing on-resistance of devices, and improve the efficiency of the devices. To be specific, for a bipolar junction device (BJT device), the presence of a buried layer may reduce the resistance of the collector and increase the characteristics frequency Ft. Moreover, the presence of an N-type heavily doped buried layer may prevent a lightly doped collector region with a thin epitaxial from being changed into a space barrier region by reverse bias voltage. For a MOS device, the presence of the buried layer increases a base region concentration of a parasitic-PNP transistor and is capable of avoiding a low impedance path “Latch-up”. Latch-up indicates a low impedance path between a power supply VDD and a ground wire GND (VSS) in a CMOS wafer, which is generated by the interaction of the parasitic PNP and NPN bipolar device. The presence of Latch-up may create a large current between the VDD and the GND.
There are mainly two traditional buried layer processes: the first process is forming a buried layer with different impurity types by performing selective implanting to the substrate through photolithography process, and the second process is achieving self alignment implanting of a buried layer by taking a low pressure deposition silicon nitride layer (LPSIN layer) as the hard mask and taking an oxide layer which grows relatively thick as the mask. The steps of these two processes will be described briefly in the following, in conjunction with the drawings.
The procedures of the first traditional buried layer process include the following steps as shown in FIGS. 1 to 6:
1. preparing a substrate 11; forming a thick oxide layer 12 on the substrate 11 by thermal oxidation process; forming an antireflection layer 13 and a photoresist layer 14; and removing portions of the oxide layer 12, antireflection layer 13, and photoresist layer 14 on a region where a first buried layer is to be implanted, by photolithography and corrosion process, thereby forming a first buried layer region pattern in the oxide layer 12 (referring to FIG. 1);
2. removing the antireflection layer 13 and the photoresist layer 14 (referring to FIG. 2);
3. forming a thin oxide layer 15 on the surface of the substrate where the first buried layer is to be implanted, by a thermal oxidation process (referring to FIG. 3);
4. forming the first buried layer 16 in the substrate through ion implanting by using the oxide layer 12 as a mask layer (referring to FIG. 4, in which the first buried layer 16 is doped with an N-type dopant, for example); and
5. removing the oxide layer 12 on the surface of the substrate where a second buried layer is to be implanted, by photolithography and corrosion process (referring to FIGS. 5); and
6. repeating steps 3 and 4 to form a second buried layer 17 in the substrate (referring to FIG. 6, in which the second buried layer is doped with a P-type dopant, for example).
In fabricating a buried layer by this method, a photolithography process is required to be carried out twice, which increases the cost of photolithography. Moreover, the development cycle of the entire process is prolonged and the overall process cost is high.
The procedures of the second traditional buried layer process include the following steps as shown in FIGS. 7 to 11:
1. preparing a substrate 21; forming a first oxide layer 22 on the substrate 21 by thermal oxidation process; depositing an LPSIN layer 23; and defining an N-type doped region by photolithography process to form a first buried layer region pattern in the LPSIN layer 23 (referring to FIG. 7);
2. implanting an N-type impurity to form a first buried layer 24 in the substrate (referring to FIG. 8);
3. forming a thick second oxide layer 25 on the first buried layer region 24 through thermal oxidation process by using the LPSIN layer 23 as a mask (referring to FIG. 9);
4. removing the LPSIN layer 23 on the region where a P-type doping is required, and implanting P-type impurity by using the second oxide layer 25 as a mask to form a second buried layer 26 in the substrate (referring to FIGS. 10); and
5. removing the first oxide layer 22 and the second oxide layer 25 (referring to FIG. 11).
In fabricating a semiconductor buried layer by this method, the thickness of the second oxide layer 25 is generally about 5800 Å; and after removing the first oxide layer 22 and the second oxide layer 25, the thickness difference (the step) between the first buried layer 24 and the second buried layer 26 is generally about 2900 Å.
Moreover, during the above buried layer processing, crystal defects may occur when a buried layer is fabricated by the second traditional buried layer process, and as a result the electrical performance of a semiconductor device may be reduced and unable to meet the design requirements.